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Testing service

Wafer level testing

Along the demand of advanced package, such as wafer level package (WLP), flip chip package (FCP), direct chip attach (DCA), system in package (SiP), and three-dimensional through-silicon via package, on the bare chip testing and necessity of avoiding the increasing package cost caused by the low yield, the test at the wafer stage plays an increasingly important role. Shanghai Sino IC has a 1000-grade purifying factory building with automatic temperature and humidity controls and can satisfy the demand of various chip wafer level testing at a maximum range.



·The dimension of the testing wafer covers 12 inches, 4, 5, 6 and 8 inches.
·Ultra-thin wafer testing, gold-back and silver-back technique, the thinnest wafer thickness of 100 um; wafer dimensions of 5, 6, 8 inches.
·Wafer level conducts high and low temperature testing from 40 below DEG C to 150 DEG C; wafer dimension covers 12 inches, 5, 6, and 8 inches.
·Bumped wafer test.
·Multi-target wafer MPW test.
·Provide user-defined inkless MAP or office ink.
Our service further includes:

·Daily report
·Week report
·Yield analysis
·Testing time optimization
·Automatic data transmission

For more information, please contact Business


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